Selected Papers by Joel W. Gannett

Network coding, an emerging field of research, provides a means to create efficient all-optical multicast networks that feature hitless reconfiguration. Here a photonic bitwise exclusive-OR hardware element supplies the key enabling functionality.

This is the presentation poster for the paper listed above, "Efficient, Fault-Tolerant All-Optical Multicast Networks via Network Coding."

Here we show how spacetime transformations consistent with the principle of relativity can be derived without an explicit assumption of the constancy of the speed of light, without gedanken experiments involving light rays, and without an assumption of differentiability, or even continuity, for the spacetime mapping. Hence, these historic results could have been derived centuries ago, even before the advent of calculus. This raises an interesting question: Could Galileo have derived Einsteinian relativity?

Traditionally, telecommunication signals are processed in the electronic domain, where generations of advances in the art of electronics provide sophisticated processing functionality. To transport telecommunication signals between electronic processing points, however, signals are beneficially converted from electrons to photons to take advantage of the huge bandwidth and relatively low cost per bit of optical transport media. Examples are networks of optical fibers, which may carry photonic signals hundreds or thousands of kilometers to facilitate long-distance communication. Ideally, such networks should keep their photonic signals in the photonic domain during their entire transit through the network, because optical-to-electronic and electronic-to-optical conversions entail costly power dissipation. However, accumulated signal impairments on long paths through optical networks may become severe enough to require clean up with complex electronic processing functionality not available in the optical domain. Hence, one or more optical-electronic-optical (OEO) conversions may be necessary on long paths. This patent addresses the question of placing OEO conversion capability strategically to minimize its use while still providing impairment-feasible (valid) paths between every pair of nodes in a network. Moreover, this patent shows how to route demands in an impairment-feasible way between any pair of nodes in the network, once the OEO resource is placed properly and parsimoniously according to our algorithm.

We have demonstrated powerful new techniques for identifying optical impairments that cause degradations in optical channels. We identify optical impairments by applying machine learning and pattern classification to eye diagrams. These techniques enable the development of low-cost optical performance monitors having significant diagnostic capabilities.

Data in the Optical Domain Networks (DOD-N) can suffer high packet drops owing to small optical buffer capacities. We present a technique to reduce packet drops that relies on the relative primeness of two integers.

This is the presentation poster for the paper listed above, "Improving Optical Data Router Performance through Prime Packet Recycling."

IP over optical network performance can be improved with dynamic bandwidth allocation, depending on the reallocation paradigm and the network topology. Under high connectivity, dynamic bandwidth allocation provides a notable boost to the network's traffic-carrying capacity.

These are the presentation viewgraphs for the paper listed above, "Performance of IP over Optical Networks with Dynamic Bandwidth Allocation."

This paper describes two key network architecture design concepts that relate to evolving existing transport networks into economically viable next-generation optical networks. Today's metropolitan transport networks largely consist of synchronous optical network/synchronous digital hierarchy rings or switch-to-switch fiber connections for some form of optical Ethernet. The result is an optical-electrical-optical infrastructure that has limited use in providing wavelength services. Wavelength-division multiplexing (WDM) is the enabling technology for wavelength services, but it has limited penetration in the metropolitan area due to its cost justification being dependent primarily on fiber relief. The first part of this paper shows how existing services, primarily using time-division-multiplexing (TDM) transport, can be used to economically justify a WDM infrastructure while achieving significantly lower costs than legacy design techniques would produce. Dynamic bandwidth-on-demand (BoD) service is another elusive goal envisioned for next-generation metropolitan networks. This paper addresses how an economically viable BoD infrastructure can be built based on revenues from existing enterprise services rather than relying on revenues from new and unproven services. Quantitative analyses, presented in the paper, show the key parameters that determine when BoD services will be used, how bandwidth granularity affects BoD decisions, and how the customer's use of BoD drives service provider network design considerations.

We address the requirements and design of bandwidth on demand networks in the context of grid services. Regardless of the deployment scenario for grid services (e.g., commercial or research), there is a need for efficient use of network facilities and a need to meet the performance requirements of the grid services users. We present quantitative analysis showing how these needs can be met.

We present a method for impairment-aware routing in transparent networks that allows constraint dependencies and objectives minimizing regeneration cost. The method is guaranteed to identify impairment-feasible paths when they exist and uses transponder resources efficiently.

This is the presentation poster for the paper listed above, "Cost-Conscious Impairment-Aware Routing."

We enhance the potential cost savings from optical network transparency by applying Connected Dominating Sets and impairment-aware routing, thus reducing the density of OEO nodes substantially below that obtained with more straightforward path improvement heuristics.

These are the presentation viewgraphs for the paper listed above, "Maximizing the Transparency Advantage in Optical Networks"

Planning and designing the next generation of IP router or switched broadband networks seems a daunting challenge considering the many complex, interacting factors affecting the performance and cost of such networks. Generally, this complexity implies that it may not even be clear what constitutes a "good" network design for a particular specification. Different network owners or operators may view the same solution differently, depending on their unique needs and perspectives. Nevertheless, we have observed a core common issue arising in the early stages of network design efforts involving leading-edge broadband switched technologies such as ATM, Frame Relay, and SMDS; or even Internet IP router networks. This core issue can be stated as follows: Given a set of service demands for the various network nodes, where should switching or routing equipment be placed to minimize the Installed First Cost of the network? Note that the specified service demands are usually projections for a future scenario and generally entail significant uncertainty. Despite this uncertainty, we have found that network owners and operators generally feel it is worthwhile to obtain high-level advice on equipment placement with a goal of minimizing Installed First Cost. This paper reports on a heuristic approach we have implemented for this problem that has evolved out of real network design projects. A tool with both a Solution Engine and an intuitive Graphical User Interface has been developed. The approach is highly efficient; for example, the tool can often handle LATA-sized networks in seconds or less on a workstation processor. By using only nodal demands rather than the more complex point-to-point demands usually required in tools of this sort, we have created an approach that is not only highly efficient, but is also a better match to real design projects in which demand data is generally scant and highly uncertain.

In electronic implementations of parallel stochastic learning neural networks, the technique used to generate noise for the neurons can be crucial. The noise sources must present uncorrelated noise simultaneously to all neurons in the system. A linear feedback shift register (LFSR) generates a pseudorandom bit stream with good noise-like properties, but using a separate LFSR for each neuron (to obtain uncorrelated noise) requires an unacceptable overhead for VLSI implementation. Here we present a method for generating multiple arbitrarily shifted pseudorandom bit streams from a single LFSR. Each bit stream is obtained by tapping the outputs of selected LFSR cells and feeding these tapped cell outputs through a set of exclusive-OR gates. This enables many neurons to share a single LFSR, resulting in an acceptably small overhead for VLSI implementation.

This paper presents the concept, its proof, several methods for finding the cell taps, and a description of a VLSI implementation.

Despite advances in CAD tools, layout errors resulting in electrical shorts between complex nets continue to cause trouble in many VLSI design projects. Locating the geometrical features causing shorts is often the most vexing problem faced during the layout verification process. Although this problem is common and important, there seems to be no published literature dealing with short location. This paper describes a new interactive CAD tool, called shortfinder, that enables the user to find such errors quickly and with minimal effort. This is accomplished by displaying a cycle-free shortest electrical path between two points indicated by the user on a graphical display of the layout. Shortfinder was implemented as a modular enhancement to an existing layout viewing program: its data structures and algorithms are described in this paper.

Rink, an automatic layout verification system intended for FET technologies, has been enhanced to handle bipolar designs. A straightforward procedure that uses Rink's parasitic capacitance extractor to solve the bipolar device identification problem is described.

As improvements in IC (Integrated Circuit) processing technology continue to reduce both defect density and minimum feature size, increasingly complex chips are being planned, designed, and fabricated. With this increase in complexity comes an even greater increase in potential testing problems: a VLSI (Very Large Scale Integrated) circuit can have tens of thousands of internal circuit nodes that cannot be directly controlled or observed from the chip's input/output pins. The task of verifying that there are no faults hidden deep inside a VLSI circuit can be formidable, and the time and effort spent on testing chips can add significantly to the cost of IC production. Here we explore a variety of design techniques that can mitigate this growing problem.

This patent, filed in 1983, addresses the difficult problem of testing complex integrated circuits. It describes an efficient technique for implementing built-in self-testing capabilities to make integrated circuits easier to test.

Definitions of passivity and losslessness are presented that apply to n-port networks that are not necessarily linear, time-invariant, or lumped; in fact, these definitions apply to any n-port that has an abstract dynamical system representation. For lumped, non-linear n-port networks that can be mathematically represented by a finite-order dynamical system, conditions for passivity and losslessness are formulated in terms of properties of the state equation function, the output function, etc. These conditions can be verified without solving the state equation, and can be viewed as non-linear generalizations of the well-known time-domain and frequency-domain passivity and losslessness conditions for linear time-invariant lumped n-port networks.

An improved nonlinear circuit model for IMPATT diodes is presented for which each element bears a simple relationship with the physical operating mechanisms inside the device. The model contains lumped nonlinear elements as well as lumped and distributed linear elements. In its most general form it incorporates various second-order effects heretofore neglected in other circuit models. These include the effects due to unequal hole and electron ionization rates, unequal hole and electron drift velocities, and carrier diffusion.